Huawei Announces Two Patents on "Chip Packaging Structure, Its Preparation Method, and Terminal Equipment"
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Update time : 2023-08-31 11:53:59
Tianyancha shows that Huawei Technology Co., Ltd. has recently added multiple patent information, including two invention patents titled "Chip Packaging Structure, Its Preparation Method, and Terminal Equipment", with publication numbers CN116648780A and CN116670808A respectively.
Among them, the CN116648780A patented chip packaging structure includes a first chip, a second chip, a first rewiring layer, a second rewiring layer, and a vertical silicon bridge; Among them, the first chip and vertical silicon bridge are arranged side by side on the first rewiring layer, the second rewiring layer is arranged on the vertical silicon bridge and the first chip, and the second chip is arranged on the second rewiring layer; The first chip is coupled to the first rewiring layer, and the second chip is coupled to the second rewiring layer; Vertical silicon bridges have silicon through holes, which prepare a large number of silicon through holes on passive wafers to complete high-density wiring. The process is mature and stable, with high reliability, and there is no risk of disconnection and short circuit yield. The second chip is vertically interconnected with the first chip through the second wiring layer, silicon through holes, and the first wiring layer. The size of the silicon through holes in the vertical silicon bridge can match the physical channel size of the second chip to achieve high-density signal interconnection.
The patented chip packaging structure of CN116670808A includes: chips; The surface of the chip has exposed multiple conductive pads; Multiple convex block structures located on multiple conductive pads, each of which includes a metal layer and one or more welding caps located on the metal layer, and at least one of the convex block structures is provided with multiple welding caps on the metal layer. The chip packaging structure provided in the application embodiment can increase the proportion of occupied area of the convex block structure on the chip by setting multiple solder caps on the metal layer of at least one convex block structure, which is conducive to dispersing the pressure of the convex block structure on the inside of the chip during the packaging manufacturing process, and can further increase the heat dissipation capacity and current passing capacity of the convex block structure.
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