

| Pin Number | Name | Function Description |
| 16 | Vcc | Positive power supply (4.75~5.25 V) |
| 8 | GND | Ground |
| 14 | CLR | Clear input (active HIGH, asynchronous operation) |
| 11 | LOAD | Load control (active LOW, preset data) |
| 5 | UP | Up-count clock (rising edge triggered) |
| 4 | DOWN | Down-count clock (rising edge triggered) |
| 15, 1, 10, 9 | A, B, C, D | Data input pins (preset count starting point) |
| 3, 2, 6, 7 | QA, QB, QC, QD | Count output pins (QA is LSB, QD is MSB) |
| 12 | CO | Carry output (outputs pulse when counting up to 9) |
| 13 | BO | Borrow output (outputs pulse when counting down to 0) |
| Feature | Specifications |
| High-Speed (fMAX) | 54 MHz (Typical) at VCC = 5 V |
| Low Power Dissipation | ICC = 4 µA (Maximum) at TA = 25 °C |
| High Noise Immunity | VNIH = VNIL = 28% VCC (Minimum) |
| Output Drive Capability | Can drive 10 LSTTL (Low Power Schottky TTL) Loads |
| Symmetrical Output Impedance | |IOH| = IOL = 4 mA (MIN.) |
| Balanced Propagation Delays | tPLH = tPHL (Symmetrical) |
| Wide Operating Voltage Range | VCC (OPR) = 2 V to 6 V |
| Pin and Function Compatibility | Compatible with 54/74LS192-193 |


| Input Signals | Function Description | Output States | |||||
| CLR | LOAD | UP | DOWN | A/B/C/D | QA/QB/QC/QD | CO (Carry) | BO (Borrow) |
| H | × | × | × | × | 0000 (Clear) | H (Invalid) | H (Invalid) |
| L | L | × | × | A/B/C/D | A/B/C/D (Load) | H | H |
| L | H | ↓ | H | × | Increment count (+1) | Outputs L pulse when counting up to 9 | H |
| L | H | H | ↓ | × | Decrement count (-1) | H | Outputs L pulse when counting down to 0 |
| L | H | H | H | × | Hold current value | H | H |
| Part Number | Counter Type | Reset Type |
| 74160 | 4-bit Decade Counter | Asynchronous Reset |
| 74162 | 4-bit Decade Counter | Synchronous Reset |
| 74190 | 4-bit Up/Down Decade Counter | Asynchronous Reset |
| 74192 | 4-bit Up/Down Decade Counter | Asynchronous Reset |