Recently, Meta announced that it will launch the first generation of its own AI inference acceleration chip (MTIA v1) to meet the needs of Meta's internal AI development and applications. The MTIA v1 chip consists of PE opcodes, on-chip cache, off-chip cache, transfer interface, and control unit in terms of architecture.
It is reported that the chip is an ASIC chip to be designed in 2020, which can be programmed to perform one or more tasks at the same time, built with TSMC 7nm process, running at 800MHz, TDP of 25W, INT8 integer computing capability of 102.4 TOPS, FP16 floating point computing capability of 51.2 TFLOPS, and is expected to be launched in The chip is expected to be available in 2025. The chip has a dedicated control subsystem running system firmware on the meta-training and inference gas pedals. The firmware manages the available compute and memory resources, communicates with the host through a dedicated host interface, and coordinates job execution on the gas pedal. The memory subsystem uses LPDDR5 as an off-chip DRAM resource that can scale up to 128 GB. The chip also has 128 MB of on-chip SRAM, shared by all PEs, providing higher bandwidth and lower latency for frequently accessed data and instructions. In addition, the grid contains 64 PEs organized in an 8x8 configuration, with PEs connected to each other and to memory blocks via a mesh network. The grid can be used as a whole to run a single job, or it can be divided into multiple sub-grids that can run independent jobs. Each PE is equipped with two processor cores (one with vector extensions) and a number of fixed function units optimized to perform critical operations such as matrix multiplication, accumulation, data shifting, and nonlinear function computation. The processor cores are based on the RISC-V open instruction set architecture (ISA) and are heavily customized to perform the necessary computational and control tasks. Each PE also has 128 KB of local SRAM memory for fast data storage and manipulation. The architecture maximizes parallelism and data reuse, which is the foundation for running workloads efficiently. The chip provides thread- and data-level parallelism (TLP and DLP), leverages instruction-level parallelism (ILP), and enables substantial memory-level parallelism (MLP) by allowing large numbers of memory requests to be processed simultaneously. AI workloads are ubiquitous in Meta and form the basis for a wide range of use cases, including content understanding, feeds, generative AI, and ad ranking, Meta officials say. These workloads run on PyTorch with best-in-class Python integration, eager pattern development, and API simplicity. Deep Learning Recommendation Models ( DLRM ) are particularly important for improving the experience across Meta services and applications. But as these models increase in size and complexity, the underlying hardware systems need to provide exponentially more memory and compute power while remaining efficient. GPUs are not always the best choice for the specific recommended workloads running at the level of efficiency required at Meta scale. Our solution to this challenge was to design a series of recommendation-specific meta-training and inference gas pedal (MTIA) ASICs. meta co-designed the first generation of ASICs based on the requirements of next-generation recommendation models and integrated them into PyTorch to create a fully optimized ranking system. In addition, Meta claims to maintain the user experience and developer efficiency offered by PyTorch's eager-mode development. Developer efficiency is a journey with continued support for PyTorch 2.0, which enhances the way PyTorch runs at the compiler level (under the hood).
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