FPGAs (field programmable logic grid arrays) are highly flexible and ideal for various applications such as smart network interface cards and telecommunications networks. AMD (formerly Xilinx) released the latest Versal FPGAs on the 27th, which are designed to be simulated and tested before the chip is built.
Rob Bauer, senior product line manager for the AMD Versal family, pointed out that through these FPGAs, chip designers can create digital twins or digital versions of upcoming ASICs or SOCs before the chip is tapered, which can help designers verify earlier start-up software development, etc. Bauer noted that as advanced packaging technology transitions to 2.5D and 3D chip architectures, this will only become more difficult for chip manufacturers. Chip designers no longer perform verification and software development for single-chip devices, but for multi-chip devices. This is also AMD's positioning for its Versal Premium VP1902. The chip measures about 77 by 77mm and has 18.50 million logic units, twice as many as the upcoming VU19P, and a dedicated Arm core for operating the control plane, as well as an onboard network to assist in debugging. AMD VP1902 is scheduled to deliver samples to customers in the third quarter, with full availability in early 2024. However, simulating modern SoCs with billions of transistors is expensive. Depending on the size and complexity of the chip, AMD said it may need to span multiple racks and dozens or even hundreds of FPGAs. While AMD's latest FPGAs are primarily aimed at chipmakers, AMD says the chips are also ideal for companies engaged in firmware development and testing, IP block and subsystem prototype development, peripheral validation, and other test cases. As for compatibility, the new chips will use the same underlying Vivado ML software development kit as the FPGA. AMD said it will work with leading EDA vendors such as Cadence, Siemens and Synopsys to add support for more advanced features.
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