The U2P* chip is the primary connection on an UltraSPARC CPU board between the UPA System Bus (including UltraSPARC Processors and Memory) and a PCI based I/O Subsystem. Its major functions are UPA port interface, PCI bus interface, processor I/O data transfers, DMA data transfers and interrupt dispatch.
Features
- Full master and slave port connection to the high - speed UltraSPARC UPA Interconnect Architecture. The UPA is a split address/data packet - switched bus which has a potential data throughput rate of over one gigabyte/sec. UPA interface is the ECC protected.
- Two physically separate PCI bus segments, with full master and slave support.
- PCI Bus A has the following features:
- 5 volt or 3.3 volt signalling.
- 64 - bit data bus.
- Compatible with the PCI Rev 2.1 Specification.
- Compatible with the PCI 66MHz extensions.
- Support for up to four master devices (at 33MHz only).
- PCI Bus B has the following features:
- 5 volt signalling.
- 64 - bit data bus.
- Compatible with the PCI Rev 2.1 Specification.
- Support for up to six master devices.
- Two separate 16 - entry streaming caches, one for each bus segment, for accelerating some kinds of PCI DVMA activity. Single IOMMU with 16 - entry TLB for mapping DVMA addresses for both busses.
- A “Mondo - Vector” Dispatch Unit, or MDU, for delivering Interrupt requests to UltraSparc CPU modules, including support for PCI interrupts from up to six total slots, as well as interrupts from on board IO devices.
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